After the successful ‘Semicon 1’ initiative, the Union Cabinet, led by Prime Minister Narendra Modi, has given the green light to the ‘Semicon 2.0’ scheme. This new scheme aims to foster a domestic semiconductor design and manufacturing ecosystem with a substantial budget of Rs 1,27,500 crore. Twelve manufacturing units have already been sanctioned, attracting investments exceeding Rs 1.64 lakh crore. These units include various fabs and packaging facilities to meet the chip demands of diverse sectors like consumer appliances, automobiles, telecommunications, and more.
Three companies, namely Micron, Kaynes, and CG Semi, have commenced commercial production out of the approved proposals. Additionally, 24 semiconductor design projects from start-ups and MSMEs have received financial support, while 105 start-ups/MSMEs have been granted access to industry-standard Electronic Design Automation (EDA) tools. The Semicon 2.0 initiative is a strategic move to enhance India’s presence in the global semiconductor arena, building on the momentum of Semicon 1.0.
The Semicon 2.0 program is structured around six key pillars. It focuses on advancing chip design capabilities by nurturing startups engaged in chip development. Furthermore, the initiative emphasizes the development of IPs and chip/system designs. Another pillar, ‘Machines and materials,’ incentivizes companies involved in essential semiconductor manufacturing components. This strategic approach aims to bolster the semiconductor industry’s sustainable growth and foster precision manufacturing in India.
The third pillar of Semicon 2.0 emphasizes the establishment of additional fabs, with the first fab set to be operational by 2028. Efforts will be directed towards attracting more manufacturers to India for chip production. The program also encourages the establishment of ATMP/OSAT units, positioning India as a favorable location for such units globally. Research and development form another crucial pillar, focusing on advancing semiconductor technologies in collaboration with leading R&D centers. Lastly, the initiative aims to enhance chip design training in universities, with a significant number of students already benefiting from advanced EDA tools.
