US-based technology giant IBM has introduced the world’s first sub-1 nanometre (nm) chip technology, a significant advancement for the semiconductor industry as it nears the limits of traditional chip scaling. The new chip, developed on a 0.7 nm process node, incorporates a unique three-dimensional transistor design known as nanostack.
This innovative chip allows for ongoing enhancements in performance and energy efficiency at atomic-scale dimensions. With nearly 100 billion transistors packed into a device the size of a fingernail, it nearly doubles the transistor density of IBM’s previously unveiled 2 nm chip technology from 2021.
IBM projects that this new technology could offer up to 50% higher performance or 70% greater energy efficiency compared to its 2 nm node chips. It is anticipated to cater to demanding applications like generative AI, cloud infrastructure, and next-generation electronic devices.
Jay Gambetta, Director of IBM Research and IBM Fellow, hailed this chip breakthrough as a significant milestone in computing, propelling technology beyond the nanometre era to the scale of atoms. The nanostack architecture employed by IBM vertically stacks and staggers transistors, allowing for more components to be integrated onto a chip while optimizing different materials for performance and power efficiency independently.
Furthermore, IBM researchers have demonstrated that this architecture can notably enhance SRAM scaling, aiding chip designers in creating more efficient processors capable of managing high-bandwidth AI workloads. IBM anticipates commercial adoption of this technology within the next five years.
The research for this groundbreaking technology was carried out at IBM’s semiconductor research facility in Albany, New York, in collaboration with industry partners such as ASML, Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions.
